Deep sub-micro technology is rapidly leading to exceedingly complex, billion-transistor chips. By these technology evolutions, a system is integrated into a chip so called a system-on-a-chip (SOC). In order to bridge the productivity gap between available transistors and able to be designed in SOC, higher-level behavioral language and design re-use become more common. However, these techniques affect test methodologies and failure analysis of SOC. On the other hand, SOCs are implementation as a collection of heterogeneous circuits such like ASICs, DRAMs and analog circuits, so it will be large impact for Design for Testability techniques (DFT) and test cost issues. To solve the complex testing issues that are arising with SOCs, we show technology requirements about following seven areas.
|出版ステータス||Published - 2001|
|イベント||4th International Conference on ASIC Proceedings - Shanghai, China|
継続期間: 2001 10月 23 → 2001 10月 25
|Conference||4th International Conference on ASIC Proceedings|
|Period||01/10/23 → 01/10/25|
ASJC Scopus subject areas