Test data compression of 100x for scan-based BIST

Masayuki Arai; Satoshi Fukumoto; Kazuhiko Iwasaki; Tatsuru Matsuo; Takahisa Hiraide; Hideaki Konishi; Michiaki Emori; Takashi Aikyo

doi:10.1109/TEST.2006.297664

Test data compression of 100x for scan-based BIST

Masayuki Arai^*, Satoshi Fukumoto, Kazuhiko Iwasaki, Tatsuru Matsuo, Takahisa Hiraide, Hideaki Konishi, Michiaki Emori, Takashi Aikyo

^*この研究の対応する著者

研究成果: Conference contribution

10 被引用数 (Scopus)

抄録

We developed a scheme for scan-based BIST that can compress test stimuli and responses by more than 100 times. The scheme is based on a scan-BIST architecture, and combines four techniques: the invert-and-shift operation, run-length compression, scan address partitioning, and LFSR pre-shifting. Our scheme achieved a 10Ox compression rate in environments where Xs do not occur without reducing the fault coverage of the original ATPG vectors. Furthermore, we enhanced the masking logic to reduce data for X-masking so that test data is still compressed to 1/100 in a practical environment where Xs occur. We applied our scheme to five real VLSI chips, and the technique compressed the test data by 100x for scan-based BIST.

本文言語	English
ホスト出版物のタイトル	2006 IEEE International Test Conference, ITC
出版社	Institute of Electrical and Electronics Engineers Inc.
ISBN（印刷版）	1424402921, 9781424402922
DOI	https://doi.org/10.1109/TEST.2006.297664
出版ステータス	Published - 2006
外部発表	はい
イベント	2006 IEEE International Test Conference, ITC - Santa Clara, CA, United States 継続期間: 2006 10月 22 → 2006 10月 27

出版物シリーズ

名前	Proceedings - International Test Conference
ISSN（印刷版）	1089-3539

Conference

Conference	2006 IEEE International Test Conference, ITC
国/地域	United States
City	Santa Clara, CA
Period	06/10/22 → 06/10/27

ASJC Scopus subject areas

電子工学および電気工学
応用数学

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10.1109/TEST.2006.297664

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引用スタイル

Arai, M, Fukumoto, S, Iwasaki, K, Matsuo, T, Hiraide, T, Konishi, H, Emori, M & Aikyo, T 2006, Test data compression of 100x for scan-based BIST. in 2006 IEEE International Test Conference, ITC., 4079342, Proceedings - International Test Conference, Institute of Electrical and Electronics Engineers Inc., 2006 IEEE International Test Conference, ITC, Santa Clara, CA, United States, 06/10/22. https://doi.org/10.1109/TEST.2006.297664

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abstract = "We developed a scheme for scan-based BIST that can compress test stimuli and responses by more than 100 times. The scheme is based on a scan-BIST architecture, and combines four techniques: the invert-and-shift operation, run-length compression, scan address partitioning, and LFSR pre-shifting. Our scheme achieved a 10Ox compression rate in environments where Xs do not occur without reducing the fault coverage of the original ATPG vectors. Furthermore, we enhanced the masking logic to reduce data for X-masking so that test data is still compressed to 1/100 in a practical environment where Xs occur. We applied our scheme to five real VLSI chips, and the technique compressed the test data by 100x for scan-based BIST.",

author = "Masayuki Arai and Satoshi Fukumoto and Kazuhiko Iwasaki and Tatsuru Matsuo and Takahisa Hiraide and Hideaki Konishi and Michiaki Emori and Takashi Aikyo",

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AU - Arai, Masayuki

AU - Fukumoto, Satoshi

AU - Iwasaki, Kazuhiko

AU - Matsuo, Tatsuru

AU - Hiraide, Takahisa

AU - Konishi, Hideaki

AU - Emori, Michiaki

AU - Aikyo, Takashi

PY - 2006

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N2 - We developed a scheme for scan-based BIST that can compress test stimuli and responses by more than 100 times. The scheme is based on a scan-BIST architecture, and combines four techniques: the invert-and-shift operation, run-length compression, scan address partitioning, and LFSR pre-shifting. Our scheme achieved a 10Ox compression rate in environments where Xs do not occur without reducing the fault coverage of the original ATPG vectors. Furthermore, we enhanced the masking logic to reduce data for X-masking so that test data is still compressed to 1/100 in a practical environment where Xs occur. We applied our scheme to five real VLSI chips, and the technique compressed the test data by 100x for scan-based BIST.

AB - We developed a scheme for scan-based BIST that can compress test stimuli and responses by more than 100 times. The scheme is based on a scan-BIST architecture, and combines four techniques: the invert-and-shift operation, run-length compression, scan address partitioning, and LFSR pre-shifting. Our scheme achieved a 10Ox compression rate in environments where Xs do not occur without reducing the fault coverage of the original ATPG vectors. Furthermore, we enhanced the masking logic to reduce data for X-masking so that test data is still compressed to 1/100 in a practical environment where Xs occur. We applied our scheme to five real VLSI chips, and the technique compressed the test data by 100x for scan-based BIST.

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PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2006 IEEE International Test Conference, ITC

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Test data compression of 100x for scan-based BIST

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出版物シリーズ

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ASJC Scopus subject areas

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