TY - GEN
T1 - Test generation and diagnostic test generation for open faults with considering adjacent lines
AU - Takahashi, Hiroshi
AU - Higami, Yoshinobu
AU - Kikkawa, Toru
AU - Aikyo, Takashi
AU - Takamatsu, Yuzo
AU - Yamazaki, Koji
AU - Tsutsumi, Toshiyuki
AU - Yotsuyanagi, Hiroyuki
AU - Hashizume, Masaki
PY - 2007
Y1 - 2007
N2 - In order to ensure high quality of DSM circuits, testing for the open defect in the circuits is necessary. However, the modeling and techniques for test generation for open faults have not been established yet. In this paper, we propose a method for generating tests and diagnostic tests based on a new open fault model. Firstly, we show a new open fault model with considering adjacent lines [9]. Under the open fault model, we reveal more about the conditions to excite the open fault. Next we propose a method for generating tests for open faults by using a stuck-at fault test with don't cares. We also propose a method for generating a diagnostic test that can distinguish the pair of open faults. Finally, experimental results show that 1) the proposed method is able to achieve 100% fault coverages for almost all benchmark circuits and 2) the proposed method is able to reduce the number of indistinguished open fault pairs.
AB - In order to ensure high quality of DSM circuits, testing for the open defect in the circuits is necessary. However, the modeling and techniques for test generation for open faults have not been established yet. In this paper, we propose a method for generating tests and diagnostic tests based on a new open fault model. Firstly, we show a new open fault model with considering adjacent lines [9]. Under the open fault model, we reveal more about the conditions to excite the open fault. Next we propose a method for generating tests for open faults by using a stuck-at fault test with don't cares. We also propose a method for generating a diagnostic test that can distinguish the pair of open faults. Finally, experimental results show that 1) the proposed method is able to achieve 100% fault coverages for almost all benchmark circuits and 2) the proposed method is able to reduce the number of indistinguished open fault pairs.
UR - http://www.scopus.com/inward/record.url?scp=57249098479&partnerID=8YFLogxK
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U2 - 10.1109/DFT.2007.11
DO - 10.1109/DFT.2007.11
M3 - Conference contribution
AN - SCOPUS:57249098479
SN - 0769528856
SN - 9780769528854
T3 - Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
SP - 243
EP - 251
BT - Proceedings - 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT 2007
T2 - 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT 2007
Y2 - 26 September 2007 through 28 September 2007
ER -