TY - GEN
T1 - Timing-aware diagnosis for small delay defects
AU - Aikyo, Takashi
AU - Takahashi, Hiroshi
AU - Higami, Yoshinobu
AU - Ootsu, Junichi
AU - Ono, Kyohei
AU - Takamatsu, Yuzo
PY - 2007
Y1 - 2007
N2 - As semiconductor technologies progress, testing of small delay defects are becoming more important for SoCs. However, fault diagnosis of small delay defects has not been developed. We propose a novel timing-aware method for diagnosing small delay defects with a small computation cost using gate delay fault simulation with the minimum detectable delay, as introduced in the statistical delay quality model. The experimental results show that the proposed method is capable of identifying fault locations for small delay defects with a small computation cost.
AB - As semiconductor technologies progress, testing of small delay defects are becoming more important for SoCs. However, fault diagnosis of small delay defects has not been developed. We propose a novel timing-aware method for diagnosing small delay defects with a small computation cost using gate delay fault simulation with the minimum detectable delay, as introduced in the statistical delay quality model. The experimental results show that the proposed method is capable of identifying fault locations for small delay defects with a small computation cost.
UR - http://www.scopus.com/inward/record.url?scp=78651225707&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=78651225707&partnerID=8YFLogxK
U2 - 10.1109/DFT.2007.30
DO - 10.1109/DFT.2007.30
M3 - Conference contribution
AN - SCOPUS:78651225707
SN - 0769528856
SN - 9780769528854
T3 - Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
SP - 223
EP - 231
BT - Proceedings - 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT 2007
T2 - 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT 2007
Y2 - 26 September 2007 through 28 September 2007
ER -