TY - JOUR
T1 - Timing verification of sequential logic circuits based on controlled multi-clock path analysis
AU - Nakamura, Kazuhiro
AU - Kimura, Shinji
AU - Takagi, Kazuyoshi
AU - Watanabe, Katsumasa
PY - 1998/1/1
Y1 - 1998/1/1
N2 - This paper introduces a new kind of false path, which is sensitizable but does not affect the decision of the maximum clock frequency. Such false paths exist in multi-clock operations controlled by waiting states, and the delay time of these paths can be greater than the clock period. This paper proposes a method to detect these waiting false paths based on the symbolic state traversal. In this method, the maximum allowable clock cycle of each path is computed using update cycles of each register.
AB - This paper introduces a new kind of false path, which is sensitizable but does not affect the decision of the maximum clock frequency. Such false paths exist in multi-clock operations controlled by waiting states, and the delay time of these paths can be greater than the clock period. This paper proposes a method to detect these waiting false paths based on the symbolic state traversal. In this method, the maximum allowable clock cycle of each path is computed using update cycles of each register.
KW - False path
KW - Maximum delay analysis
KW - Multiple clock operation
KW - Timing verification
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M3 - Article
AN - SCOPUS:0032305823
SN - 0916-8508
VL - E81-A
SP - 2515
EP - 2520
JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
IS - 12
ER -