TY - JOUR

T1 - Topology optimization of conductors in electrical circuit

AU - Nomura, Katsuya

AU - Yamasaki, Shintaro

AU - Yaji, Kentaro

AU - Bo, Hiroki

AU - Takahashi, Atsuhiro

AU - Kojima, Takashi

AU - Fujita, Kikuo

N1 - Publisher Copyright:
© 2019, Springer-Verlag GmbH Germany, part of Springer Nature.

PY - 2019/6/15

Y1 - 2019/6/15

N2 - This study proposes a topology optimization method for realizing a free-form design of conductors in electrical circuits. Conductors in a circuit must connect components, such as voltage sources, resistors, capacitors, and inductors, according to the given circuit diagram. The shape of conductors has a strong effect on the high-frequency performance of a circuit due to parasitic circuit elements such as parasitic inductance and capacitance. In this study, we apply topology optimization to the design of such conductors to minimize parasitic effects with maximum flexibility of shape manipulation. However, when the distribution of conductors is repeatedly updated in topology optimization, disconnections and connections of conductors that cause open and short circuits, respectively, may occur. To prevent this, a method that uses fictitious electric current and electric field calculations is proposed. Disallowed disconnections are prevented by limiting the maximum value of the fictitious current density in conductors where a current is induced. This concept is based on the fact that an electric current becomes concentrated in a thin conductor before disconnection occurs. Disallowed connections are prevented by limiting the maximum value of the fictitious electric field strength around conductors where a voltage is applied. This is based on the fact that the electric field in a parallel plate capacitor is inversely proportional to the distance between the plates. These limitations are aggregated as a single constraint using the Kreisselmeier-Steinhauser function in the formulation of optimization problems. This constraint prevents only disallowed disconnections and connections, but does not prevent allowed topology changes. The effectiveness of the constraint is confirmed using simple examples, and an actual design problem involving conductors in electromagnetic interference filters is used to verify that the proposed constraint can be utilized for conductor optimization.

AB - This study proposes a topology optimization method for realizing a free-form design of conductors in electrical circuits. Conductors in a circuit must connect components, such as voltage sources, resistors, capacitors, and inductors, according to the given circuit diagram. The shape of conductors has a strong effect on the high-frequency performance of a circuit due to parasitic circuit elements such as parasitic inductance and capacitance. In this study, we apply topology optimization to the design of such conductors to minimize parasitic effects with maximum flexibility of shape manipulation. However, when the distribution of conductors is repeatedly updated in topology optimization, disconnections and connections of conductors that cause open and short circuits, respectively, may occur. To prevent this, a method that uses fictitious electric current and electric field calculations is proposed. Disallowed disconnections are prevented by limiting the maximum value of the fictitious current density in conductors where a current is induced. This concept is based on the fact that an electric current becomes concentrated in a thin conductor before disconnection occurs. Disallowed connections are prevented by limiting the maximum value of the fictitious electric field strength around conductors where a voltage is applied. This is based on the fact that the electric field in a parallel plate capacitor is inversely proportional to the distance between the plates. These limitations are aggregated as a single constraint using the Kreisselmeier-Steinhauser function in the formulation of optimization problems. This constraint prevents only disallowed disconnections and connections, but does not prevent allowed topology changes. The effectiveness of the constraint is confirmed using simple examples, and an actual design problem involving conductors in electromagnetic interference filters is used to verify that the proposed constraint can be utilized for conductor optimization.

KW - Conductor

KW - Electrical circuit

KW - Electromagnetic interference filter

KW - Geometric constraint

KW - Topology optimization

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U2 - 10.1007/s00158-018-02187-2

DO - 10.1007/s00158-018-02187-2

M3 - Article

AN - SCOPUS:85059887096

SN - 1615-147X

VL - 59

SP - 2205

EP - 2225

JO - Structural and Multidisciplinary Optimization

JF - Structural and Multidisciplinary Optimization

IS - 6

ER -