Ultra-high-speed and low-power SOI CMOS technology with body-tied hybrid trench isolation structure

Yuuichi Hirano; Takashi Ipposhi; Dang Hai Thai; Toshiaki Iwamatsu; Tatsuhiko Ikeda; Mikio Tsujiuchi; Shigeto Maegawa; Masahide Inuishi; Yuzuru Ohji

Ultra-high-speed and low-power SOI CMOS technology with body-tied hybrid trench isolation structure

Yuuichi Hirano^*, Takashi Ipposhi, Dang Hai Thai, Toshiaki Iwamatsu, Tatsuhiko Ikeda, Mikio Tsujiuchi, Shigeto Maegawa, Masahide Inuishi, Yuzuru Ohji

^*この研究の対応する著者

研究成果: Paper › 査読

1 被引用数 (Scopus)

抄録

The hybrid-trench-isolation (HTI) SOI technology overcomes the scaling limitations caused by the difficulty of the gate thinning. A high-speed and low-power microcontroller including logic, memory, analog, and PLL circuits has been demonstrated by using the HTI SOI technology with bulk-layout compatibility. Over 10Gbps and low-noise operation with excellent eye patterns of output buffer circuits were also obtained for ultra-high-speed network LSIs. It is also verified that low-voltage and high-speed operation is achieved for an Actively Body-bias Controlled (ABC) SOI SRAM that has a new cell structure connecting the bodies of the access and the driver transistors with the word line. It is concluded that the SOI technology with the HTI structure is one of the solutions against the scaling limitations.

本文言語	English
ページ	60-64
ページ数	5
出版ステータス	Published - 2004
外部発表	はい
イベント	Dielectrics for Nanosystems: Materials Science, Processing, Reliability, and Manufacturing - Proceedings of the First International Symposium - Honolulu, HI, United States 継続期間: 2004 10月 3 → 2004 10月 8

Other

Other	Dielectrics for Nanosystems: Materials Science, Processing, Reliability, and Manufacturing - Proceedings of the First International Symposium
国/地域	United States
City	Honolulu, HI
Period	04/10/3 → 04/10/8

ASJC Scopus subject areas

工学（全般）

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引用スタイル

Hirano, Y., Ipposhi, T., Thai, D. H., Iwamatsu, T., Ikeda, T., Tsujiuchi, M., Maegawa, S., Inuishi, M., & Ohji, Y. (2004). Ultra-high-speed and low-power SOI CMOS technology with body-tied hybrid trench isolation structure. 60-64. Paper presented at Dielectrics for Nanosystems: Materials Science, Processing, Reliability, and Manufacturing - Proceedings of the First International Symposium, Honolulu, HI, United States.

Ultra-high-speed and low-power SOI CMOS technology with body-tied hybrid trench isolation structure. / Hirano, Yuuichi; Ipposhi, Takashi; Thai, Dang Hai その他.
2004. 60-64 Paper presented at Dielectrics for Nanosystems: Materials Science, Processing, Reliability, and Manufacturing - Proceedings of the First International Symposium, Honolulu, HI, United States.

研究成果: Paper › 査読

Hirano, Y, Ipposhi, T, Thai, DH, Iwamatsu, T, Ikeda, T, Tsujiuchi, M, Maegawa, S, Inuishi, M & Ohji, Y 2004, 'Ultra-high-speed and low-power SOI CMOS technology with body-tied hybrid trench isolation structure', Paper presented at Dielectrics for Nanosystems: Materials Science, Processing, Reliability, and Manufacturing - Proceedings of the First International Symposium, Honolulu, HI, United States, 04/10/3 - 04/10/8 pp. 60-64.

Hirano Y, Ipposhi T, Thai DH, Iwamatsu T, Ikeda T, Tsujiuchi M その他. Ultra-high-speed and low-power SOI CMOS technology with body-tied hybrid trench isolation structure. 2004. Paper presented at Dielectrics for Nanosystems: Materials Science, Processing, Reliability, and Manufacturing - Proceedings of the First International Symposium, Honolulu, HI, United States.

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abstract = "The hybrid-trench-isolation (HTI) SOI technology overcomes the scaling limitations caused by the difficulty of the gate thinning. A high-speed and low-power microcontroller including logic, memory, analog, and PLL circuits has been demonstrated by using the HTI SOI technology with bulk-layout compatibility. Over 10Gbps and low-noise operation with excellent eye patterns of output buffer circuits were also obtained for ultra-high-speed network LSIs. It is also verified that low-voltage and high-speed operation is achieved for an Actively Body-bias Controlled (ABC) SOI SRAM that has a new cell structure connecting the bodies of the access and the driver transistors with the word line. It is concluded that the SOI technology with the HTI structure is one of the solutions against the scaling limitations.",

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AU - Hirano, Yuuichi

AU - Ipposhi, Takashi

AU - Thai, Dang Hai

AU - Iwamatsu, Toshiaki

AU - Ikeda, Tatsuhiko

AU - Tsujiuchi, Mikio

AU - Maegawa, Shigeto

AU - Inuishi, Masahide

AU - Ohji, Yuzuru

PY - 2004

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AB - The hybrid-trench-isolation (HTI) SOI technology overcomes the scaling limitations caused by the difficulty of the gate thinning. A high-speed and low-power microcontroller including logic, memory, analog, and PLL circuits has been demonstrated by using the HTI SOI technology with bulk-layout compatibility. Over 10Gbps and low-noise operation with excellent eye patterns of output buffer circuits were also obtained for ultra-high-speed network LSIs. It is also verified that low-voltage and high-speed operation is achieved for an Actively Body-bias Controlled (ABC) SOI SRAM that has a new cell structure connecting the bodies of the access and the driver transistors with the word line. It is concluded that the SOI technology with the HTI structure is one of the solutions against the scaling limitations.

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Ultra-high-speed and low-power SOI CMOS technology with body-tied hybrid trench isolation structure

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