抄録
The authors describe an LSI that was developed for wide application in digital video signal processing. The LSI consists of two independent 12-bit full adder/subtracters and a variable delay unit. The minimum arithmetic operation cycle time is 67 ns and the power dissipation is 250 mW. The LSI is packaged in a 135-pin RIT package. It has a rather simple structure, but has very powerful applications in real-time video signal processing. The application of this LSI to a TV conferencing codec is presented.
| 本文言語 | English |
|---|---|
| ページ（範囲） | 809-812 |
| ページ数 | 4 |
| ジャーナル | Unknown Journal |
| 出版ステータス | Published - 1986 |
ASJC Scopus subject areas
- 信号処理
- 電子工学および電気工学
- 音響学および超音波学