VLSI architecture for a flexible motion estimation with parameters

J. Choi; Nozomu Togawa; Masao Yanagisawa; T. Ohtsuki

doi:10.1109/ASPDAC.2002.994962

VLSI architecture for a flexible motion estimation with parameters

J. Choi, Nozomu Togawa, Masao Yanagisawa, T. Ohtsuki

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

If motion estimation can choose the most suitable algorithm according to the changing characteristics of input image signals, we can obtain benefits, which improve quality and performance, reduce power consumption and optimize the system. In this paper we propose a reconfigurable approach to the motion estimation algorithm and architecture. The proposed algorithm determines motion type and then selects an adapted algorithm in order to improve the quality and performance of images. We implemented the flexible and reconfigurable architecture by hardware with an address generator unit, delay unit, and parameters. Our architecture supports more than one block-matching algorithm and parameters providing an optimized system. We are implementing our architecture by using hardware description language (VHDL) and synthesis design tools. We analyze the performance of architecture and present adaption to the algorithm for a low cost real time application.

本文言語	English
ホスト出版物のタイトル	Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
出版社	Institute of Electrical and Electronics Engineers Inc.
ページ	452-457
ページ数	6
ISBN（印刷版）	0769514413, 9780769514413
DOI	https://doi.org/10.1109/ASPDAC.2002.994962
出版ステータス	Published - 2002
イベント	7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002 - Bangalore, India 継続期間: 2002 1月 7 → 2002 1月 11

Other

Other	7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
国/地域	India
City	Bangalore
Period	02/1/7 → 02/1/11

ASJC Scopus subject areas

コンピュータグラフィックスおよびコンピュータ支援設計
ハードウェアとアーキテクチャ
電子工学および電気工学

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10.1109/ASPDAC.2002.994962

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引用スタイル

Choi, J., Togawa, N., Yanagisawa, M., & Ohtsuki, T. (2002). VLSI architecture for a flexible motion estimation with parameters. In Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002 (pp. 452-457). Article 994962 Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2002.994962

VLSI architecture for a flexible motion estimation with parameters. / Choi, J.; Togawa, Nozomu ; Yanagisawa, Masao その他.
Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002. Institute of Electrical and Electronics Engineers Inc., 2002. p. 452-457 994962.

研究成果: Conference contribution

Choi, J, Togawa, N , Yanagisawa, M & Ohtsuki, T 2002, VLSI architecture for a flexible motion estimation with parameters. in Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002., 994962, Institute of Electrical and Electronics Engineers Inc., pp. 452-457, 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002, Bangalore, India, 02/1/7. https://doi.org/10.1109/ASPDAC.2002.994962

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VLSI architecture for a flexible motion estimation with parameters

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