VLSI architecture for variable block size motion estimation in H.264/AVC with low cost memory organization

Yang Song; Zhenyu Liu; Takeshi Ikenaga; Satoshi Goto

doi:10.1109/VDAT.2006.258131

VLSI architecture for variable block size motion estimation in H.264/AVC with low cost memory organization

Yang Song^*, Zhenyu Liu, Takeshi Ikenaga, Satoshi Goto

^*この研究の対応する著者

大学院情報生産システム研究科

研究成果: Conference contribution

7 被引用数 (Scopus)

抄録

A 1-D full search variable block sizes motion estimation (VBSME) architecture is presented in this paper. By properly choosing the partial sum of absolute differences (SAD) registers and scheduling the add operations, the architecture can be implemented with simple control logic and regular workflow. Moreover, only one single-port SRAM is required to store the search area and then reduces 72.7% hardware cost of SRAM. The design is realized with TSMC 0.18μm 1P6M technology with a hardware cost of 67.6K gates. In typical working condition (1.8V, 25°C), a clock frequency of 266MHz can be achieved.

本文言語	English
ホスト出版物のタイトル	2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers
ページ	89-92
ページ数	4
DOI	https://doi.org/10.1109/VDAT.2006.258131
出版ステータス	Published - 2007 10月 1
イベント	2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Hsinchu, Taiwan, Province of China 継続期間: 2007 4月 26 → 2007 4月 28

出版物シリーズ

名前	2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers

Conference

Conference	2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006
国/地域	Taiwan, Province of China
City	Hsinchu
Period	07/4/26 → 07/4/28

ASJC Scopus subject areas

ハードウェアとアーキテクチャ
電子工学および電気工学

文献へのアクセス

10.1109/VDAT.2006.258131

他のファイルとリンク

引用スタイル

Song, Y., Liu, Z., Ikenaga, T., & Goto, S. (2007). VLSI architecture for variable block size motion estimation in H.264/AVC with low cost memory organization. In 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers (pp. 89-92). Article 4027503 (2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers). https://doi.org/10.1109/VDAT.2006.258131

VLSI architecture for variable block size motion estimation in H.264/AVC with low cost memory organization. / Song, Yang; Liu, Zhenyu; Ikenaga, Takeshi その他.
2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers. 2007. p. 89-92 4027503 (2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers).

研究成果: Conference contribution

Song, Y, Liu, Z, Ikenaga, T & Goto, S 2007, VLSI architecture for variable block size motion estimation in H.264/AVC with low cost memory organization. in 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers., 4027503, 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers, pp. 89-92, 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006, Hsinchu, Taiwan, Province of China, 07/4/26. https://doi.org/10.1109/VDAT.2006.258131

Song Y, Liu Z, Ikenaga T, Goto S. VLSI architecture for variable block size motion estimation in H.264/AVC with low cost memory organization. In 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers. 2007. p. 89-92. 4027503. (2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers). doi: 10.1109/VDAT.2006.258131

Song, Yang ; Liu, Zhenyu ; Ikenaga, Takeshi その他. / VLSI architecture for variable block size motion estimation in H.264/AVC with low cost memory organization. 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers. 2007. pp. 89-92 (2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers).

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abstract = "A 1-D full search variable block sizes motion estimation (VBSME) architecture is presented in this paper. By properly choosing the partial sum of absolute differences (SAD) registers and scheduling the add operations, the architecture can be implemented with simple control logic and regular workflow. Moreover, only one single-port SRAM is required to store the search area and then reduces 72.7% hardware cost of SRAM. The design is realized with TSMC 0.18μm 1P6M technology with a hardware cost of 67.6K gates. In typical working condition (1.8V, 25°C), a clock frequency of 266MHz can be achieved.",

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VLSI architecture for variable block size motion estimation in H.264/AVC with low cost memory organization

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出版物シリーズ

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