VLSI architecture of a low complexity face detection algorithm for real-time video encoding

Tianruo Zhang; Minghui Wang; Chen Liu; Satoshi Goto

doi:10.1109/ASICON.2009.5351587

VLSI architecture of a low complexity face detection algorithm for real-time video encoding

Tianruo Zhang^*, Minghui Wang, Chen Liu, Satoshi Goto

^*この研究の対応する著者

研究成果: Conference contribution

抄録

Combining video encoder and content analyzer to improve the encoding efficiency by content-aware algorithms is very challenging now. For the aiming application of low cost hardware real-time encoder with face detectionfor videophone, this paper proposes a face detection algorithm to detect each macroblock (MB) as one part of a face or not. This face detection algorithm has a unique estimation-and-verification process and can be combined with a H264 encoder by MB level pipeline architecture. 97.91% MBs in faces can be detected. VLSl architecture of proposed face detection algorithm is designed and an area of 4.3k gates is achieved. Power consumption is only 1.45mW at 100MHz. The detection speed achieves 1315fps in ClF sequences.

本文言語	English
ホスト出版物のタイトル	ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC
ページ	147-150
ページ数	4
DOI	https://doi.org/10.1109/ASICON.2009.5351587
出版ステータス	Published - 2009
イベント	2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha 継続期間: 2009 10月 20 → 2009 10月 23

Other

Other	2009 8th IEEE International Conference on ASIC, ASICON 2009
City	Changsha
Period	09/10/20 → 09/10/23

ASJC Scopus subject areas

ハードウェアとアーキテクチャ
電子工学および電気工学

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10.1109/ASICON.2009.5351587

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title = "VLSI architecture of a low complexity face detection algorithm for real-time video encoding",

abstract = "Combining video encoder and content analyzer to improve the encoding efficiency by content-aware algorithms is very challenging now. For the aiming application of low cost hardware real-time encoder with face detectionfor videophone, this paper proposes a face detection algorithm to detect each macroblock (MB) as one part of a face or not. This face detection algorithm has a unique estimation-and-verification process and can be combined with a H264 encoder by MB level pipeline architecture. 97.91% MBs in faces can be detected. VLSl architecture of proposed face detection algorithm is designed and an area of 4.3k gates is achieved. Power consumption is only 1.45mW at 100MHz. The detection speed achieves 1315fps in ClF sequences.",

keywords = "Face detection, VLSI architecture",

author = "Tianruo Zhang and Minghui Wang and Chen Liu and Satoshi Goto",

year = "2009",

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pages = "147--150",

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AU - Wang, Minghui

AU - Liu, Chen

AU - Goto, Satoshi

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AB - Combining video encoder and content analyzer to improve the encoding efficiency by content-aware algorithms is very challenging now. For the aiming application of low cost hardware real-time encoder with face detectionfor videophone, this paper proposes a face detection algorithm to detect each macroblock (MB) as one part of a face or not. This face detection algorithm has a unique estimation-and-verification process and can be combined with a H264 encoder by MB level pipeline architecture. 97.91% MBs in faces can be detected. VLSl architecture of proposed face detection algorithm is designed and an area of 4.3k gates is achieved. Power consumption is only 1.45mW at 100MHz. The detection speed achieves 1315fps in ClF sequences.

KW - Face detection

KW - VLSI architecture

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BT - ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC

T2 - 2009 8th IEEE International Conference on ASIC, ASICON 2009

Y2 - 20 October 2009 through 23 October 2009

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VLSI architecture of a low complexity face detection algorithm for real-time video encoding

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