抄録
A CMOS VLSI chip set, which consists of three chips including a chip with 495,000 transistors, 0.8-ns gate delay, and a 12-ns RAM, has been developed to achieve a high-performance 32-bit mainframe processor. This chip set uses a 1.2-μm double-diffused-drain transistor, double-layer metallization technology and a sophisticated CAD (computer-aided design) system. Each chip is mounted on a 288-pin surface-mount pin grid array package. A one-board CPU can be realized by assembling the chip set on a multilayer printed wiring board with RAMs and interface LSIs.
本文言語 | English |
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ページ(範囲) | 24.6/1-4 |
ジャーナル | Proceedings of the Custom Integrated Circuits Conference |
出版ステータス | Published - 1988 |
外部発表 | はい |
ASJC Scopus subject areas
- 電子工学および電気工学