TY - GEN
T1 - Voltage-island driven floorplanning considering level-shifter positions
AU - Yu, Bei
AU - Dong, Sheqin
AU - Goto, Satoshi
AU - Chen, Song
PY - 2009
Y1 - 2009
N2 - Power optimization has become a significant issue when the CMOS technology entered the nanometer era. Multiple-Supply Voltage (MSV) is a popular and effective method for power reduction. Level shifters may cause area and Interconnect Length Overhead(ILO), and should be considered during floorplanning and post-floorplanning stages. In this paper, we propose a two phases framework VLSAF to solve voltage and level shifter assignment problem. At floorplanning phase, we use: a convex cost network flow algorithm to assign voltage; a minimum cost flow algorithm to assign level shifter. At post-floorplanning phase, a heuristic method is adopted to redistribute white spaces and calculate the positions and shapes of level shifters. Experimental results show VLSAF is effective.
AB - Power optimization has become a significant issue when the CMOS technology entered the nanometer era. Multiple-Supply Voltage (MSV) is a popular and effective method for power reduction. Level shifters may cause area and Interconnect Length Overhead(ILO), and should be considered during floorplanning and post-floorplanning stages. In this paper, we propose a two phases framework VLSAF to solve voltage and level shifter assignment problem. At floorplanning phase, we use: a convex cost network flow algorithm to assign voltage; a minimum cost flow algorithm to assign level shifter. At post-floorplanning phase, a heuristic method is adopted to redistribute white spaces and calculate the positions and shapes of level shifters. Experimental results show VLSAF is effective.
KW - Convex Network Flow
KW - Level Shifter Assignment
KW - Voltage Assignment
KW - Voltage-Island
KW - White Space Redistribution
UR - http://www.scopus.com/inward/record.url?scp=70350586572&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=70350586572&partnerID=8YFLogxK
U2 - 10.1145/1531542.1531558
DO - 10.1145/1531542.1531558
M3 - Conference contribution
AN - SCOPUS:70350586572
SN - 9781605585222
SP - 51
EP - 56
BT - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
T2 - 19th ACM Great Lakes Symposium on VLSI, GLSVLSI '09
Y2 - 10 May 2009 through 12 May 2009
ER -