Voltage island-driven power optimization for application specific network-on-chip design

Kan Wang; Sheqin Dong; Satoshi Goto

doi:10.1145/2206781.2206823

Voltage island-driven power optimization for application specific network-on-chip design

Kan Wang^*, Sheqin Dong, Satoshi Goto

^*この研究の対応する著者

早稲田大学

研究成果: Conference contribution

6 被引用数 (Scopus)

抄録

In this paper, a voltage island aware framework is proposed for low power design of application specific NoC (LPASNoC). Through a three-phase processing including voltage island generation, VI-driven floorplanning and post-floorplan processing, the total power consumption, design cost and total wire length can be optimized. Experimental results show that compared to traditional ASNoC, the proposed method can reduce total core power by about 34.5% and chip area by about 26.8% without increasing communication power.

本文言語	English
ホスト出版物のタイトル	Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
ページ	171-176
ページ数	6
DOI	https://doi.org/10.1145/2206781.2206823
出版ステータス	Published - 2012
イベント	22nd Great Lakes Symposium on VLSI, GLSVLSI'2012 - Salt Lake City, UT 継続期間: 2012 5月 3 → 2012 5月 4

Other

Other	22nd Great Lakes Symposium on VLSI, GLSVLSI'2012
City	Salt Lake City, UT
Period	12/5/3 → 12/5/4

ASJC Scopus subject areas

工学（全般）

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10.1145/2206781.2206823

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title = "Voltage island-driven power optimization for application specific network-on-chip design",

abstract = "In this paper, a voltage island aware framework is proposed for low power design of application specific NoC (LPASNoC). Through a three-phase processing including voltage island generation, VI-driven floorplanning and post-floorplan processing, the total power consumption, design cost and total wire length can be optimized. Experimental results show that compared to traditional ASNoC, the proposed method can reduce total core power by about 34.5% and chip area by about 26.8% without increasing communication power.",

keywords = "Application specific NoC, Multiple supply voltages, Network components, Power consumption, Voltage island",

author = "Kan Wang and Sheqin Dong and Satoshi Goto",

year = "2012",

doi = "10.1145/2206781.2206823",

language = "English",

isbn = "9781450312448",

pages = "171--176",

booktitle = "Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI",

note = "22nd Great Lakes Symposium on VLSI, GLSVLSI'2012 ; Conference date: 03-05-2012 Through 04-05-2012",

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T1 - Voltage island-driven power optimization for application specific network-on-chip design

AU - Wang, Kan

AU - Dong, Sheqin

AU - Goto, Satoshi

PY - 2012

Y1 - 2012

N2 - In this paper, a voltage island aware framework is proposed for low power design of application specific NoC (LPASNoC). Through a three-phase processing including voltage island generation, VI-driven floorplanning and post-floorplan processing, the total power consumption, design cost and total wire length can be optimized. Experimental results show that compared to traditional ASNoC, the proposed method can reduce total core power by about 34.5% and chip area by about 26.8% without increasing communication power.

AB - In this paper, a voltage island aware framework is proposed for low power design of application specific NoC (LPASNoC). Through a three-phase processing including voltage island generation, VI-driven floorplanning and post-floorplan processing, the total power consumption, design cost and total wire length can be optimized. Experimental results show that compared to traditional ASNoC, the proposed method can reduce total core power by about 34.5% and chip area by about 26.8% without increasing communication power.

KW - Application specific NoC

KW - Multiple supply voltages

KW - Network components

KW - Power consumption

KW - Voltage island

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DO - 10.1145/2206781.2206823

M3 - Conference contribution

AN - SCOPUS:84861123143

SN - 9781450312448

SP - 171

EP - 176

BT - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

T2 - 22nd Great Lakes Symposium on VLSI, GLSVLSI'2012

Y2 - 3 May 2012 through 4 May 2012

ER -

Voltage island-driven power optimization for application specific network-on-chip design

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