TY - JOUR

T1 - Waiting false path analysis of sequential logic circuits for performance optimization

AU - Nakamura, Kazuhiro

AU - Takagi, Kazuyoshi

AU - Kimura, Shinji

AU - Watanabe, Katsumasa

PY - 1998

Y1 - 1998

N2 - This paper introduces a new class of false path, which is sensitizable but does not affect the decision of the clock period. We call such false paths waiting false paths, which correspond to multi-cycle operations controlled by wait states. The allowable delay time of waiting false paths is greater than the clock period. When the number of allowable clock cycles for each path is determined, the delay of the path can be the product of the clock period and the allowable cycles. This paper presents a method to analyze allowable cycles and to detect waiting false paths based on symbolic traversal of FSM. We have applied our method to 30 ISCAS89 FSM benchmarks and found that 22 circuits include such paths. 11 circuits among them include such paths which are critical paths, where the delay is measured as the number of gates on the path. Information on such paths can be used in the logic synthesis to reduce the number of gates and in the layout synthesis to reduce the size of gates.

AB - This paper introduces a new class of false path, which is sensitizable but does not affect the decision of the clock period. We call such false paths waiting false paths, which correspond to multi-cycle operations controlled by wait states. The allowable delay time of waiting false paths is greater than the clock period. When the number of allowable clock cycles for each path is determined, the delay of the path can be the product of the clock period and the allowable cycles. This paper presents a method to analyze allowable cycles and to detect waiting false paths based on symbolic traversal of FSM. We have applied our method to 30 ISCAS89 FSM benchmarks and found that 22 circuits include such paths. 11 circuits among them include such paths which are critical paths, where the delay is measured as the number of gates on the path. Information on such paths can be used in the logic synthesis to reduce the number of gates and in the layout synthesis to reduce the size of gates.

UR - http://www.scopus.com/inward/record.url?scp=0032318394&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0032318394&partnerID=8YFLogxK

U2 - 10.1145/288548.289059

DO - 10.1145/288548.289059

M3 - Conference article

AN - SCOPUS:0032318394

SN - 1092-3152

SP - 392

EP - 395

JO - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

JF - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

T2 - Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, ICCAD

Y2 - 8 November 1998 through 12 November 1998

ER -