Flip-chip package provides the highest chip density because I/O buffers in it could be placed anywhere inside a chip. The assignment of bump pads, I/O buffers and I/O pins will affect the satisfaction of timing requirement inside die core. In this paper, we proposed an effective three-step hierarchical approach to satisfy the timing-constrained I/O buffer placement in an area-I/O flip-chip design, meanwhile, wirelength could be optimized. First of all, I/O buffers are inserted to the floorplan plane greedily, and then, the wirelength between I/O buffers and I/O pins are optimized by a fixed-outline floorplanning algorithm. Secondly, a network flow model is conducted, and a min-cost-max-flow algorithm is used to assign I/O pins, I/O buffers and bump pads. Finally, the timing constraints are translated to length constraints, the results that satisfy timing constraints are selected. The experimental results show that, under the given timing constraints, higher timing-constrained satisfaction ratio (TCSR) is obtained, and the reduction of total wirelength is 14% on average.
|ホスト出版物のタイトル||IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS|
|出版ステータス||Published - 2012|
|イベント||2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012 - Kaohsiung|
継続期間: 2012 12月 2 → 2012 12月 5
|Other||2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012|
|Period||12/12/2 → 12/12/5|
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